consecutive instructionの例文
- Instruction decoding and execution were pipelined, to allow overlapping processing of consecutive instructions in a program.
- RISC-V guarantees forward progress ( no live-lock ) if the code follows rules on the timing and sequence of instructions : 1 ) It must use only the " I " subset . 2 ) To prevent repetitive cache misses, the code ( including the retry loop ) must occupy no more than 16 consecutive instructions . 3 ) It must not include any system or fence instructions, or taken backward branches between the lr and sc . 4 ) The backward branch to the retry loop must be to the original sequence.
